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MODULE CODE

1module simple_and (

2input wire a,

3input wire b,

4output wire y

5);

6assign y = a & b;

7endmodule

TEST BENCH

1module testbench;

2reg a, b;

3wire y;

5simple_and uut (

6.a(a), .b(b), .y(y)

7);

9initial begin

10a = 0; b = 0; #10;

11a = 0; b = 1; #10;

12a = 1; b = 0; #10;

13a = 1; b = 1; #10;

14end

15endmodule

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Features

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Our comprehensive platform provides all the tools you need to learn digital design, from basic logic gates to complex sequential circuits.

Interactive Code Editor

Monaco Editor with Verilog syntax highlighting, auto-completion, and error detection.

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Progressive Problem Sets

Structured learning path from basic gates to complex digital systems.

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